1. Recent developments in the automated design and analysis of digital systems;Breuer,1972
2. The effects of races, delays and delay faults on test generation;Breuer;IEEE Trans. Comput.,1974
3. Variable mesh simulator;Kelly,1968
4. Logic circuit simulation using S/360 CSMP;Mathews;Simulation,1970
5. A model and implementation of a universal time delay simulator for large digital nets;Szygenda,1970