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Optimization of novel superjunction LDMOS with partial low K layer

  • Published:2018-11 Issue: Volume:123 Page:226-233
  • ISSN:0749-6036
  • Container-title:Superlattices and Microstructures
  • language:en
  • Short-container-title:Superlattices and Microstructures

Author:

Wu LijuanORCID,Zhang Yinyan,Yang Hang,Song YueORCID,Yuan Na,Lei Bing,Hu LiminORCID,Wu Yiqing

Funder

National Natural Science Foundation of China

Scientific Research Fund of Hunan Provincial Education Department

talents project of Changsha University of Science & Technology

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

Reference21 articles.

1. Ultralow on -resistance SOI LDMOS with three separated gates and high-k dielectric;Luo;IEEE Trans. Electron. Dev.,2016

2. Breakdown voltage analysis for a step buried oxide SOI structure;Duan;Chin. J. Semicond.,2005

3. Super Junction LDMOST in Silicon-on-sapphire Technology (SJ-LDMOST);Nassif-Khalil,2002

4. Back-etched Super-junction LDMOST on SOI;Honarkhah,2004

5. Super-junction LDMOST on a silicon-on-sapphire substrate;Nassif-Khalil;IEEE Trans. Electron. Dev.,2003

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1. A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study;Semiconductor Science and Technology;2024-05-20

2. A Novel High Performance SOI LDMOS with Buried Stepped Gate Field Plate;Transactions on Electrical and Electronic Materials;2023-09-30

3. Analysis of Gate Oxides in LDMOS for Radiation Hardening Against SEGR;2022 International Conference on Intelligent Controller and Computing for Smart Power (ICICCSP);2022-07-21

4. Study of TID Radiation Effects on the Breakdown Voltage of Buried P-Pillar SOI LDMOSFETs;IEEE Transactions on Device and Materials Reliability;2021-09

5. Novel Self-Modulated Lateral Superjunction Device Suppressing the Inherent 3-D JFET Effect;IEEE Electron Device Letters;2020-09
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