Energy-efficient and security-optimized AES hardware design for ubiquitous computing

Author:

Yicheng Chen,Xuecheng Zou,Zhenglin Liu,Yu Han,Zhaoxia Zheng

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

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3. A Low Delay AES Round Transform Architecture Using Constant Matrix Multiplications Merging Technologies;2022 IEEE 17th Conference on Industrial Electronics and Applications (ICIEA);2022-12-16

4. Unified coprocessor for high-speed AES-128 and SM4 encryption;2022 IEEE 6th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC );2022-10-03

5. FPGA Implementation of High-Performance s-box Model and Bit-level Masking for AES Cryptosystem;International Journal of Electrical and Electronics Research;2022-06-30

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