Numerical analysis of SOI LDMOS using a recessed source and a trench drain-Reference-Cited by-同舟云学术

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Numerical analysis of SOI LDMOS using a recessed source and a trench drain

Published:2000-12 Issue:11-12 Volume:31 Page:963-967
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Yoo S.-J,Kim S.-H,Choi Y.-I,Chung S.-K

Publisher

Elsevier BV

Subject

General Engineering

Reference4 articles.

1. S. Matsumoto, H. Yoshino, Device simulation of a thin-film SOI power MOSFET for structure optimization, SSDM extended abstracts, 1993, pp. 276–278.

2. Smart Power ICs;Murari,1996

3. Breakdown voltage in LDMOS transistors using internal field rings;Nezar;IEEE Trans. Electron. Devices,1991

4. E.S. Vera, N. Yamashita, T. Yachi, A novel power MOSFET using drench trench technology, ISPSD, 1992, pp. 294–299.

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A high voltage SOI pLDMOS with a partial interface equipotential floating buried layer;Journal of Semiconductors;2013-07

2. Optimization of high voltage LDMOSFETs with complex multiple-resistivity drift region and field plate;Microelectronics Reliability;2010-07

3. A new double gate SOI LDMOS with a step doping profile in the drift region;Journal of Semiconductors;2009-08

4. Bulk silicon CDMOS technology for an advanced PDP data drvier IC;2008 9th International Conference on Solid-State and Integrated-Circuit Technology;2008-10

5. High-voltage power integrated circuit technology using bulk-silicon for plasma display panels data driver IC;Microelectronic Engineering;2004-01

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