A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs
Author:
Publisher
Elsevier BV
Subject
Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science
Reference24 articles.
1. Suppression of drain-current overshoot in SOI-MOSFETs using an ultrathin SOI substrate
2. A high speed 0.6- mu m 16 K CMOS gate array on a thin SIMOX film
3. Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film
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1. A suggested nanoscale partially depleted SOI-MOSFET (PDSOI) by built-in tunneling diodes- improvement on short channel effects and frequency features;Materials Science and Engineering: B;2023-10
2. A nanoscale junctionless FET to amend the electric field distribution using a β-Ga2O3 packet;Journal of Materials Science: Materials in Electronics;2023-08
3. Complete depletion area in SOI junctionless FETs by multiple buried P-type pockets;The European Physical Journal Plus;2023-06-14
4. Pyramid P+ area in SOI junction-less MOSFET for logic applications: DC investigation;Applied Nanoscience;2023-03-02
5. Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer;physica status solidi (a);2022-03-29
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