Voltage difference engineering in SOI MOSFETs: A novel side gate device with improved electrical performance
Author:
Publisher
Elsevier BV
Subject
Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science
Reference11 articles.
1. Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET for deep sub-0.1-μm channel regime
2. Two-Dimensional Analytical Modeling of Fully Depleted DMG SOI MOSFET and Evidence for Diminished SCEs
3. A novel subthreshold slope technique for the extraction of the buried-oxide interface trap density in the fully depleted SOI MOSFET
4. Design guideline for minimum channel length in silicon-on-insulator (SOI) mosfet
5. The Localized-SOI MOSFET as a Candidate for Analog/RF Applications
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Novel Nanoscale FD-SOI MOSFET with Energy Barrier and Heat-Sink Engineering for Enhanced Electric Field Uniformity;Micro and Nanostructures;2024-09
2. Introducing a buried pure silicon layer in SOI-MESFET transistor to increase the breakdown voltage by modifying carriers and electric field distribution;Emergent Materials;2023-02-20
3. Comparison of the performance improvement for the two novel SOI-tunnel FETs with the lateral dual-gate and triple-gate;Microsystem Technologies;2018-07-30
4. Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL;Microsystem Technologies;2017-09-08
5. High performance multi-channel MOSFET on InGaAs for RF amplifiers;Superlattices and Microstructures;2017-02
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