Effects of thermal annealing on the interface between tungsten and CeO 2 /La 2 O 3 stack gate dielectrics

Author:

Zhang Jieqiong,Wong Hei,Kakushima Kuniyuki,Iwai Hiroshi

Funder

Council of Hong Kong, Hong Kong

Publisher

Elsevier BV

Subject

Surfaces, Coatings and Films,Condensed Matter Physics,Instrumentation

Reference31 articles.

1. Nano-CMOS Gate Dielectric Engineering;Wong,2012

2. On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology;Wong;Microelectron. Eng.,2015

3. Gate stack high-κ materials for Si-based MOSFETs past, present, and futures;Mohsenifar;Microelectron. Solid State Electron.,2015

4. High-k materials and metal gates for CMOS applications;Robertson;Mater. Sci. Eng. R Rep.,2015

5. Advantage of further scaling in gate dielectrics below 0.5 nm of equivalent oxide thickness with La2O3 gate dielectrics;Kakushima;Microelectron. Reliab,2010

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