Technology towards low power/low voltage and scaling of MOSFETs

Author:

Iwai Hiroshi,Momose Hisayo Sasaki

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference34 articles.

1. Prospects for low-power, high-speed MPUs using 1.5 nm direct-tunneling gate oxide MOSFETs;Momose;J. Solid State Electrons,1997

2. A low power chip set for portable multimedia applications;Chandrakasan,1994

3. Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment;Matsuzawa;J. Solid State Circuits,1994

4. Low-power CMOS digital design;Chandrakasan;J. Solid State Circuits,1992

5. Adiabatic computing with “N-2ND logic family”;Kramer,1994

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1. Si Nanowire FET Technology;ECS Transactions;2011-04-25

2. CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING;International Journal of High Speed Electronics and Systems;2006-03

3. An MOS transistor model for RF IC design valid in all regions of operation;IEEE Transactions on Microwave Theory and Techniques;2002

4. A design system for RFIC: challenges and solutions;Proceedings of the IEEE;2000-10

5. Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime;IEEE Transactions on Electron Devices;2000-07

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