Energy-aware and fault-tolerant custom topology design method for network-on-chips-Reference-Cited by-同舟云学术

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Energy-aware and fault-tolerant custom topology design method for network-on-chips

Published:2019-03 Issue: Volume:19 Page:54-66
ISSN:1878-7789
Container-title:Nano Communication Networks
language:en
Short-container-title:Nano Communication Networks

Author:

Kullu Pinar^ORCID,Tosun Suleyman^ORCID

Funder

The Scientific and Technological Research Council of TurkeyThe Scientific and Technological Research Council of Turkey (TUBITAK)

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Applied Mathematics,Computer Networks and Communications

Reference39 articles.

1. Network on chip: an architecture for billion transistor era;Hemani,2000

2. Route packets not wires: on-chip interconnection networks;Dally,2001

3. Networks on chips: a new soc paradigm;Benini;Computer,2002

4. Principles and Practices of Interconnection Networks;Dally,2004

5. Networks on Chip, Vol. 396;Jantsch,2003

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1. Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey;Microprocessors and Microsystems;2023-11

2. An Artificial Bee Colony Based Mapping Method for Three Dimensional Network-on-Chip;2023 International Conference on Emerging Trends in Networks and Computer Communications (ETNCC);2023-08-16

3. Novel fault tolerance topology using corvus seek algorithm for application specific NoC;Integration;2023-03

4. A new adaptive selection strategy for reducing latency in networks on chip;Integration;2023-03

5. Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture;Integration;2023-03

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