OPAIC: An optimization technique to improve energy consumption and performance in application specific network on chips

Author:

Taassori Mehdi,Taassori Meysam,Niroomand Sadegh,Vizvári Béla,Uysal Sener,Hadi-Vencheh Abdollah

Publisher

Elsevier BV

Subject

Applied Mathematics,Electrical and Electronic Engineering,Condensed Matter Physics,Instrumentation

Reference32 articles.

1. International Technology Roadmap for Semiconductors (ITRS), 2010.

2. Networks on chips: A New SoCParadigm;Benini;Computer,2002

3. G. De Micheli, C. Seiculescu, S. Murali, L. Benini, F. Angiolini, A. Pullini, Networks on Chips: from research to products, in: Proceedings of DAC, 2010, pp. 300–305.

4. Jalabert, S. Murali, L. Benini, G. De Micheli, ×pipesCompiler: a tool for instantiating application specific Networks on Chip, in: Proceedings of DATE, 2004, pp. 884–889.

5. Linear Programming Based Techniques for Synthesis of Network-on-Chip Architectures, IEEE Transaction On Very Large Scale Integration (VLSI);Srinivasan;System,2006

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