EDISYN: A Language-Based Editor for High-level Synthesis11This work was supported by NSF grant CCR-9058180

Author:

Chang Chee-Keng,Brown Geoffrey M.,Leeser Miriam E.

Publisher

Elsevier

Reference17 articles.

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2. Instruction Set Processor Specifications (ISPS): The Notation and Its Applications;Barbacci;IEEE Transactions on Computers,1981

3. O. A. Buset and M. I. Elmasry. ACE: A Hierarchical Graphical Interface for Architectural Synthesis. In Proceedings of the 26th Design Automation Conference. ACM and IEEE, 1989.

4. Synthesizing Correct Sequential Circuits;Brown,1990

5. R. L. Blackburn, D. E. Thomas, and P. M. Koenig. CORAL II: Linking Behavior and Structure in an IC Design System. In Proceedings of the 25th Design Automation Conference. ACM and IEEE, 1988.

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. High level synthesis and generating FPGAs with the BEDROC system;Journal of VLSI signal processing systems for signal, image and video technology;1993-08

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