1. Paul Stanford and Paul Mancuso,Electronic Design Interchange Format Version 2 00, Electronic Industries Organization, second edition, 1989.
2. High Level Synthesis Workshop, “High level synthesis workshop benchmark set,” 1991, Obtained by ftp from mcnc .org.
3. Chia-Jeng Tseng and Daniel P. Siewiorek, “Automated synthesis of data paths in digital systems,”IEEE Transaction on Computer-Aided Design, vol. CAD-5, pp. 379–395, 1986.
4. P. Dewilde, E. Deprettere and R. Nouta, “Parallel and pipelined VLSI implementation of signal processing algorithms,” S.Y. Kung, H.J. Whitehouse and T. Kailath, eds.,VLSI and Modern Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1985, Chap. 15, pp. 257–275.
5. Houria Oudghiri and Bozena Kaminska, “Global weighted scheduling and allocation algorithms,”Proceedings of 1992 European Design Automation Conference, IEEE Computer Society Press, Los Alamitas, CA, March 1992.