1. Gate length scalability of n-MOSFET's down to 30 nm: Comparison between LDD and non-LDD structures;Murakami;IEEE Trans Electron Devices,2000
2. High performance metal gate MOSFET's for 0.1 μm regime;Yagishita;IEEE Trans Electron Devices,2000
3. Ono A, Fukasaka K, Matsuda T, Fukai T, Ikezawa N, Imai K, et al. A 70 nm gate length CMOS technology with 1.0 V operation. In: 2000 Symp. VLSI Tech. Digest, Honolulu. June 13–15, 2000. p. 14–15
4. Hu JC, Chatterjee A, Mehrota M, Xu J, Shiau WT, Rodder M. Sub-0.1 mm CMOS with source/drain extension spacer formed using nitrogen implantation prior to thick gate re-oxidation. In: 2000 Symp. VLSI Tech. Digest, Honolulu. June 13–15, 2000. p. 188–9
5. Song S, Kim WS, Lee JS, Choe TH, Choi JH, Kang MS, et al. Design of sub-100 nm CMOSFETs: Gate dielectrics and channel engineering. In: 2000 Symp. VLSI Tech. Digest, Honolulu. June 13–15, 2000. p. 190–1