Gate length scalability of n-MOSFETs down to 30 nm: Comparison between LDD and non-LDD structures

Author:

Murakami E.,Yoshimura T.,Goto Y.,Kimura S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Case study on asymmetric Id measured on MOSFET;2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA);2020-07-20

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3. Impact of LDD Depth Variations on the Performance Characteristics of SONOS NAND Flash Device;IEEE Transactions on Device and Materials Reliability;2016-09

4. Simulation Results for Nanoscale Field Effect Diode;IEEE Transactions on Electron Devices;2007-03

5. High performance GaAs MESFETs with molecular implanted and optimized lowly-doped drain structure for maximized speed, gain and breakdown performance;Solid-State Electronics;2005-12

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