POPS: A tool for delay/power performance optimization
Author:
Publisher
Elsevier BV
Subject
Hardware and Architecture,Software
Reference22 articles.
1. Power consicious CAD tools and methodologies: A perspective;Singh;Proc. IEEE,1995
2. M. Borah, R.M. Owens, M.J. Irwin, Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint, in: ISLPD'95 Symposium Proceedings, pp. 167–172
3. Efficient timing analysis for CMOS circuits considering data dependent delays;Sun;IEEE Trans. CAD Int. Circuits Syst.,1998
4. Critical path selection for performance optimization;Chen;IEEE Trans. CAD Int. Circuits Syst.,1995
5. S.S. Sapatnekar, W. Chuang, Power vs delay in gate sizing: conflicting objectives, in: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1995, pp. 463–466
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