Design Optimization with Automated Cell Generation

Author:

Landrault A.,Azémard N.,Maurine P.,Robert M.,Auvergne D.

Publisher

Springer Berlin Heidelberg

Reference17 articles.

1. Dally, W.J., Chang, A.: The role of custom design in ASIC chips. In: Proc. 37th design automation Conference, pp. 643–647 (2000)

2. Reis, Reis, R., Auvergne, D., Robert, M.: The Library Free Technology Mapping Problem. IWLS 2, 7.1.1–7.1.5 (1997)

3. Landrault, Pellier, L., Richard, A., Jay, C., Robert, M., Auvergne, D.: An I.P. Migration and Prototyping Strategy Using Transistor Level Synthesis. In: DCIS 2003, XVIII Design of Circuits and Integrated Systems Conference, Ciudad Real, Espagne, November 19-21, pp. 266–271 (2003)

4. Azemard, N., Auvergne, D.: POPS: A tool for delay/power performance optimization. Journal of Systems Architecture (47), 375–382 (2001)

5. McMillen, D., Butts, M., Composano, R., Hill, D., Williams, T.W.: An Industrial View of Electronic Design Automation. IEEE Transactions on Computer 19(12), 1428–1448 (2000)

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