1. PLL frequency synthesizer with multi-phase detector;Sumi;IEICE Trans. Fundam.,1999
2. A 200-MHz CMOS phase-locked loop with dual phase detectors;Ware;IEEE J. Solid State Circuits,1989
3. Optimal design of PLL with two separate phase detectors;Heiman;IEEE Trans. Commun.,1981
4. A 1.5V 250MHz to 3.0V 622MHz operation CMOS phase-locked loop with precharge type phase frequency detector;Kondoh;IEICE Trans. Electron.,1995
5. A low power 622MHz CMOS phase-locked loop with source coupled VCO and dynamic PFD;Yoshizawa;IEICE Trans. Fundam.,1997