A methodology for implementing decimator FIR filters on FPGA

Author:

Harize Saliha,Benouaret Mohamed,Doghmane Noureddine

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference12 articles.

1. A. Croisier, D.J. Esteban, M.E. Levilion, V. Rizo, Digital filter for pcm encoded signals. U.S. patent 3,777,130, April 1973.

2. A new hardware realization of digital filters;Peled;IEEE Trans Acoust Speech Signal Process,1974

3. Design and FPGA implementation of modified distributive arithmetic based DWT–IDWT processor for image compression;Nagabushanam,2011

4. Area-efficient FIR filter design on FPGAs using distributed arithmetic;Longa;IEEE Int Symp Signal Process Inform Technol,2006

5. A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting;Kotteri;IEEE Trans Circuit Syst-II: Express Briefs,2005

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