A 11.42-ENOB 6.02 fJ/conversion-step SAR-assisted digital-slope ADC with a reset-in-time VCO-based comparator for power reduction
Author:
Funder
National Natural Science Foundation of China
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering
Reference20 articles.
1. 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information;Nasiri;AEU-Int J Electron Commun,2018
2. An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes;Verma;IEEE J Solid-State Circ,2007
3. A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area and parasitic capacitance effect;Aghdami;AEU-Int J Electron Commun,2022
4. An early shutdown circuit for power reduction in high-precision dynamic comparators;Shahpari;AEU-Int J Electron Commun,2020
5. An ultra low-voltage rail-to-rail comparator for on-chip energy harvesters;Nagy;AEU-Int J Electron Commun,2019
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