A low-power rail-to-rail input-range linear delay element circuit

Author:

Rivandi Hassan,Ebrahimi Sudeh,Saberi Mehdi

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference17 articles.

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2. A, 100-kS/s 8.3-ENOB 1.7-time-domain analog-to-digital converter;Kim;IEEE Trans Circuits Syst II: Exp Briefs,2014

3. 5-bit 5-GS/s noninterleaved time-based ADC in 65-nm CMOS for radio-astronomy applications;Xu;IEEE Trans Very Large Scale Integr (VLSI) Syst,2016

4. Low power high resolution CMOS variable-delay element;El Mourabit;AEU-Int J Electron Commun,2011

5. Architectures of delay line ADC and delay cells for digital DC-DC converters;Wang,2013

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