Efficient integrated bus coding scheme for low-power I/O-Reference-Cited by-同舟云学术

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Efficient integrated bus coding scheme for low-power I/O

Published:2017-12 Issue: Volume:82 Page:30-36
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Supon Tareq Muhammad,Basith Iftekhar Ibne,Abdel-Raheem Esam,Rashidzadeh Rashid

Funder

Natural Sciences and Engineering Research Council (NSERC) of Canada

CMC Microsystems

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference19 articles.

1. Power consumption estimation in CMOS VLSI chips;Liu;IEEE J Solid-State Circ,1994

2. Power efficient SRAM design with integrated bit line charge pump;Wang;AEU-Int J Electron Commun,2016

3. Fast physical design of CMOS ROs for optimal performance using constrained NSGA-II;Rout;AEU-Int J Electron Commun,2015

4. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits;Veendrick;IEEE J. Solid-State Circ,1984

5. Noise reduction using low weight and constant weight coding techniques, Tech. rep.;Tabor,1990

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Improved Low-Power Coding for Serial Network-On-Chip Links;Circuits, Systems, and Signal Processing;2019-08-13

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