A 7 bit, 3 GHz bandwidth random-time-interleaved-hybrid DAC using a novel self-healing structure for DCE in 65 nm CMOS technology

Author:

Sariri Hossein,Torkzadeh Pooya,Sadughi Sirous

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference34 articles.

1. Yi S-C. A 10-bit current-steering CMOS digital to analog converter. Int J Electron Commun (AEU); 2014. https://dx.doi.org/10.1016/j.aeue.2014.07.010.

2. A 14-b, 100- MS/s CMOS DAC designed for spectral performance;Bugeja;IEEE J. SSC,1999

3. A self-trimming 14-b 100-MS/s CMOS DAC;Bugeja;IEEE J. SSC,2000

4. Kosunen M, Halonen K. Sampling jitter and power supply interference in current-steering D/A converters. Proc 2005 Eur Conf Circuit Theory Design 2005; 1, I/305–I/308.

5. Adaptive cancellation of static and dynamic mismatch error in continuous-time DACs;Kong;IEEE TCAS I, Reg Papers,2018

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