Digital background calibration of ultra-high-speed time-interleaved of PAM4 2-bit DACs
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering
Reference9 articles.
1. An interleaved full nyquist high-speed DAC technique;Olieman;IEEE J Solid-State Circuits,2015
2. A 10-b 120-M sample/s time-interleaved;Jamal;IEEE J Solid-State Circuits,2002
3. A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration;El-Chammas;IEEE J Solid-State Circuits,2011
4. A background sample-time error calibration technique using random data for wide-band high-resolution time-interleaved ADCs;Haftbaradaran;IEEE Trans Circuits Syst II, Exp Breifs,2008
5. Explicit analysis of channel mismatch effects in time-interleaved ADC systems;Kurosawa;IEEE Trans Circuits Syst I, Fundam Theory Appl,2001
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1. A Proof-of-Concept Study of Time-Interleaved Sdm-Based Dacs with Analog Multiplexing;2024
2. 200 Gb/s PAM4 modulator design without DAC for inter Data-Centre Communication;Optical and Quantum Electronics;2022-09-08
3. A 7 bit, 3 GHz bandwidth random-time-interleaved-hybrid DAC using a novel self-healing structure for DCE in 65 nm CMOS technology;AEU - International Journal of Electronics and Communications;2021-05
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