Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications-Reference-Cited by-同舟云学术

Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications

Published:2024-05 Issue: Volume:179 Page:155314
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Pathakamuri Anil Kumar,Pandey Chandan Kumar

Publisher

Elsevier BV

Reference37 articles.

1. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec;Choi;IEEE Electron Device Lett,2007

2. Numerical investigations of nanowire gate-all-around negative capacitance GaAs/InN tunnel FET;Mazumder;IEEE Access,2022

3. Pathkamuri, A. K., & Pandey, C. K. (2023). Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET. Physica Scripta. Aug 31. 2023.

4. Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects;Ashok;Phys Scr,2024

5. Design and investigation of a novel gate-all-around vertical tunnel FET with improved DC and analog/RF parameters;Karthik;ECS Journal of SolidState Science and Technology,2022

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Interfacial charge and temperature analysis of gate-all-around line tunneling TFET for improved device reliability;Physica Scripta;2024-07-02

2. Performance analysis of highly sensitive vertical tunnel FET for detecting light in near-IR range;Journal of Materials Science: Materials in Electronics;2024-06