A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur-Reference-Cited by-同舟云学术

A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

Published:2018-02 Issue: Volume:85 Page:23-31
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Li Xiaoqiang,Zhang Jingwei,Zhang Yuanzhi,Wang Wenshen,Liu Huimin,Lu Chao

Funder

Tianjin Science and Technology Committee

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference22 articles.

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2. Wang B, Zhang J, Ngoya E. A reference spur estimation method for integer-N PLLs. In: IEEE international conference on ASIC; 2013. p. 1–4.

3. Keaveney M, Walsh P, Tuthill M, Lyden C, Hunt B. A 10µs fast switching PLL synthesizer for a GSM/EDGE base-station. In: IEEE international solid-state circuits conference; 2004. p. 192–3.

4. A 0.4-V 90∼350-MHz PLL with an active loop-filter charge pump;Moon;IEEE Trans Circuits Syst II,2014

5. A digital calibration technique for charge pumps in phase-locked systems;Liang;IEEE J Solid-State Circuits,2008

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