1. A methodology for the design of testable VLSI chips;Breuer,1985
2. A knowledge based system for designing testable VLSI chips;Abadir;IEEE Design Test Comput.,1985
3. Constructing optimal test schedules for VLSI circuits having built-in test hardware;Abadir,1985
4. Design for testability—A survey;Williams;IEEE Trans Comput.,1982
5. A knowledge based system for selecting a test methodology for a PLA;Breuer,1985