A 210fs RMS jitter 187.5 MHz-3GHz fractional-N frequency synthesizer with quantization noise suppression techniques and chopping differential charge pump for SDR applications

Author:

Li Haoming,Shen Yupeng,Wang Tengjia,Liu Jiarui

Publisher

Elsevier BV

Subject

General Engineering

Reference18 articles.

1. An integrated 0.6-4.6 GHz, 5-7GHz, 10-14 GHz, and 20-28 GHz frequency synthesizer for software-defined radio applications;Osmany;IEEE J. Solid State Circuits,2010

2. A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz frequency synthesizer for software-defined radios in 0.13-μm CMOS process;Rong;IEEE Trans. Circuits and Systems-II: Express Briefs,2016

3. Very wide range frequency synthesizer architecture for avionic SDR applications;Ismaili,2015

4. Analysis and key specifications of a novel frequency synthesizer architecture for multi-standard transceivers;Van Driessche,2006

5. Analytical phase noise modeling and charge pump optimization for fractional-N PLL;Frank;IEEE Trans. Circuits and System-I: Regular Papers,2010

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