A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications-Reference-Cited by-同舟云学术

A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

Published:2022-06-14 Issue:4 Volume:65 Page:975-980
ISSN:0895-2477
Container-title:Microwave and Optical Technology Letters
language:en
Short-container-title:Micro & Optical Tech Letters

Author:

Zhou Pizeng¹^ORCID,Li Chao²^ORCID,Kang Zehui¹^ORCID,Zheng Shiyuan¹,Wu Liang¹^ORCID,Xue Quan²^ORCID

Affiliation:

1. The School of Science and Engineering and the Future Network of Intelligence Institute The Chinese University of Hong Kong, Shenzhen Shenzhen China

2. The Guangdong Provincial Key Laboratory of Millimeter‐Wave and Terahertz, Electronic and Information Engineering South China University of Technology Guangzhou China

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/mop.33368

Reference15 articles.

1. A Review of 5G Power Amplifier Design at cm-Wave and mm-Wave Frequencies

2. 19.2 A PVT-robust −39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers

3. A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture

4. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

5. Evaluation of 5 G waveform candidates considering hardware impairments and above 6 GHz operation;Wang H;2017 IEEE 85th Veh Technol Conf (VTC Spring),2017

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