Implementation of low-voltage static RAM with enhanced data stability and circuit speed-Reference-Cited by-同舟云学术

Implementation of low-voltage static RAM with enhanced data stability and circuit speed

Published:2009-06 Issue:6 Volume:40 Page:944-951
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Chung Yeonbae,Song Seung-Ho

Publisher

Elsevier BV

Subject

General Engineering

Reference16 articles.

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3. K. Takeda, et al., Redefinition of write margin for next-generation SRAM and write-margin monitoring circuit, in: IEEE International Solid-State Circuits Conference (2006) 2602–2611.

4. A 3GHz 70Mb SRAM in 65nm CMOS technology with integrated column-based dynamic power supply;Zhang;IEEE Journal of Solid-State Circuits,2006

5. 0.4V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme;Yamaoka;IEEE Journal of Solid-State Circuits,2004

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