A sub-harmonic injection locking clock multiplier with FLL PVT calibrator
Author:
Funder
Analog Devices
Carleton University
CMC Microsystems
Publisher
Elsevier BV
Subject
General Engineering
Reference27 articles.
1. A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS;Cooms,2017
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3. A distributed oscillator based all-digital PLL with a 32-phase embedded phase-to-digital converter;Takinami;IEEE J. Solid State Circ.,2011
4. A/D conversion using asynchronous delta-sigma modulation and time-to-digital conversion;Daniels;IEEE Transactions on Circuits and Systems I: Regular Papers,2010
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Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL Using Aperture Phase Detector-Based DLL Windowing Technique;IEEE Access;2023
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