Designing of low-power data oriented adders-Reference-Cited by-同舟云学术

Designing of low-power data oriented adders

Published:2014-09 Issue:9 Volume:45 Page:1177-1186
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Brzozowski Ireneusz,Kos Andrzej

Funder

National Science Centre Poland

Publisher

Elsevier BV

Subject

General Engineering

Reference18 articles.

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3. I. Brzozowski, d. Pałys, A. Kos, An analysis of full adder cells for low-power data oriented adders design, in: Proceedings of the International Conference on MIXDES, Gdynia, Poland, June, 2013.

4. Integrated Circuit Design;Weste,2010

5. Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5fJ/stage PDP;Tajalli;Microelectron. J.,2009

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