A 12-bit 1.25 GS/s RF sampling pipelined ADC using a bandwidth-expanded residue amplifier with bias-free gain-boost technique-Reference-Cited by-同舟云学术

A 12-bit 1.25 GS/s RF sampling pipelined ADC using a bandwidth-expanded residue amplifier with bias-free gain-boost technique

Published:2022-12 Issue: Volume:130 Page:105611
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Zhang Chenghao,Wei Jiangbo,Yang Yihang,Liu Maliang^ORCID

Funder

Fundamental Research Funds for the Central Universities

National Natural Science Foundation of China

Xidian University

Publisher

Elsevier BV

Subject

General Engineering

Reference23 articles.

1. A 13Bit 5GS/S ADC with time-interleaved chopping calibration in 16NM FinFET;Vaz,2018

2. A 12-b 18-GS/s RF sampling ADC with an integrated wideband track-and-hold amplifier and background calibration;Ali,2020

3. A 1.6-GS/s 12.2-mW seven-/eight-way split time-interleaved SAR ADC achieving 54.2-dB SNDR with digital background timing mismatch calibration;Guo,2020

4. A 12-bit time-interleaved 400-MS/s pipelined ADC with split-ADC digital background calibration in 4,000 conversions/channel;Hung,2019

5. A time-interleaved SAR ADC with bypass-based opportunistic adaptive calibration;Fan,2020

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS;Microelectronics Journal;2024-04

2. A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS;Microelectronics Journal;2024-04

3. Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm;Microelectronics Journal;2023-09