Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits

Author:

Sarhan Hossam,Thuries Sebastien,Billoint Olivier,Clermidy Fabien

Publisher

Elsevier BV

Subject

General Engineering

Reference25 articles.

1. Semiconductor industry association, The International Technology Roadmap for Semiconductors (ITRS), 2011 Ed.

2. Processor design in 3D die-stacking technologies;Loh;IEEE Micro,2007

3. D. Dutoit, C. Bernard, S. Cheramy, F. Clermidy, Y. Thonnart, P. Vivet, C. Freund, V.Guerin, S. Guilhot, S. Lecomte, et al., A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3DIC NoC-based MPSoC, in: Proceedings of the Symposium on VLSI Technology (VLSIT), IEEE, 2013, pp. C22–C23.

4. M. Wordeman, J. Silberman, G. Maier, Michael Scheuermann, A 3D system prototype of an eDRAM cache stacked over processor-like logic using throughsilicon vias, in: Proceedings of the Solid-State Circuits Conference Digest of Technical Papers (ISSCC), IEEE International, 2012, pp. 186–187.

5. A chip-stacked memory for on-chip sram-rich socs and processors;Saito;IEEE J. Solid-State Circuits,2010

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