Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS

Author:

B Dinesh Kumar,Pandey Sumit K.,Gupta Navneet,Shrimali Hitesh

Funder

Ministry of Electronics and Information technology

Publisher

Elsevier BV

Subject

General Engineering

Reference39 articles.

1. Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40 nm-CMOS;Jiang,2010

2. A 1.2 V 2.64 GS/s 8-bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN;Kundu,2014

3. CMOS Analog Circuit Design. Oxford Series in Electrical and Computer Engineering;Allen,2002

4. CMOS Circuit Design, Layout, and Simulation;Jacob Baker,2004

5. A 5 GS/s 10-b 76 mW time-interleaved SAR ADC in 28 nm CMOS;Fang;IEEE Trans. Circuits Syst. (TCAS)-I,2017

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5. Realization of a variable resolution modified semiflash ADC based on bit segmentation scheme;Facta universitatis - series: Electronics and Energetics;2022

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