Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors
Author:
Publisher
Elsevier BV
Subject
General Engineering
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1. Power and performance analysis of 3D network-on-chip architectures;Computers & Electrical Engineering;2020-05
2. First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip;IEEE Transactions on Computers;2018-10-01
3. Impact of TSV location in HVIC on CMOS operation: A mixed-mode TCAD simulation study;Microelectronics Journal;2018-05
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