Design of a LVTSCR triggered SCR device for low voltage ESD protection
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Publisher
Elsevier BV
Reference18 articles.
1. Investigation and design of on-chip power-rail ESD clamp circuits without suffering latchup-like failure during system-level ESD test;Ker;IEEE J. Solid State Circ.,2008
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3. A low-voltage triggering SCR for on-chip ESD protection at output and input pads;Chatterjee;IEEE Electron. Device Lett.,1991
4. Using an SCR as ESD protection without latch-up danger;Notermans;Microelectron. Reliab.,1997
5. High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps;Vashchenko;IEEE Trans. Device Mater. Reliab.,2004
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