Asynchronous switching for low-power networks-on-chip-Reference-Cited by-同舟云学术

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Asynchronous switching for low-power networks-on-chip

Published:2011-12 Issue:12 Volume:42 Page:1370-1379
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

El-Moursy Magdy A.,Shawkey Heba A.

Publisher

Elsevier BV

Subject

General Engineering

Reference36 articles.

1. A network on chip architecture and design methodology;Kumar,2002

2. Route packets, not wires: on-chip interconnection networks;Dally,2001

3. A generic architecture for on-chip packet-switched interconnections;Guerrier,2000

4. An interconnect architecture for networking systems on chips;Karim;IEEE Micro,2002

5. Networks on chips: a new SoC paradigm;Benini;IEEE Comput.,2002

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Retracted: Power macro-modeling technique for NoC-based homogeneous layered 3D ICs;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2017-11-16

2. Power Analysis Approach for NoC-based Homogeneous Stacked 3D ICs;Journal of Circuits, Systems and Computers;2017-09-11

3. WITHDRAWN: Power modeling for high performance network-on-chip architectures;Microprocessors and Microsystems;2017-05

4. Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip;Journal of Parallel and Distributed Computing;2017-04

5. High Throughput Asynchronous NoC Design under High Process Variation;Integration;2015-03

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