Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature-Reference-Cited by-同舟云学术

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature

Published:2008-12 Issue:12 Volume:39 Page:1461-1468
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Venkataratnam A.,Goel A.K.

Publisher

Elsevier BV

Subject

General Engineering

Reference9 articles.

1. Overview of nanoelectronic devices;Gordan;Proc. IEEE,1997

2. Single-electron devices and their application;Likharev;Proc. IEEE,1999

3. A. Venkataratnam, A.K. Goel, Simulation of logic circuits based on the single electron technology, in: Proceedings of the 12th International Workshop on the Physics of Semiconductor Devices, Chennai, India, December 2003.

4. A. Venkataratnam, A.K. Goel, CMOS architectures for NOR and NAND logic gates using single electron transistors, in: Proceedings of the 2005 NSTI Nanotechnology Conference, May 8–12, Anaheim, CA, 2005.

5. Design and simulation of logic gates using single electron transistors at room temperature;Venkataratnam;Int. J. Comput. Sci. Eng.,2006

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