1. Three-dimensional Integrated Circuit Design;Pavlidis,2009
2. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration;Banerjee;Proceedings of the IEEE,2001
3. Patrick Leduc, L. Di Cioccio, B. Charlet, M. Rousseau, M. Assous, D. Bouchu, A. Roule, M. Zussy, P. Gueguen, A. Roman, O. Rozeau, M. Heitzmann, J.-P. Nieto, L. Vandroux, P.-H. Haumesser, R. Quenouillere, A. Toffoli, P. Sixt, S. Maitrejean, L. Clavelier, N. Sillon, Enabling technologies for 3D chip stacking, in: Proceedings of the VLSI Technology, Systems and Applications, 21–23 April, Taiwan, 2008, pp. 76–78.
4. L. Di Cioccio, P. Gueguen, F. Grossi, P. Leduc, B. Charlet, M. Assous, A. Mathewson, J. Brun, D. Henry, P. Batude, P. Coudrain, N. Sillon, L. Clavelier, G. Poupon, M. Scannell, Proceedings of the Fourth International Conference and Exhibition on Device Packaging, IMAPS, Scottsdale, 2008.
5. RF characterization and modelling of high density through silicon vias for 3D chip stacking;Cadix;Microelectronic Engineering,2010