Improving circuit performance with multispeculative additive trees in high-level synthesis

Author:

Del Barrio Alberto A.,Hermida Román,Memik Seda Ogrenci,Mendías José M.,Molina María C.

Publisher

Elsevier BV

Subject

General Engineering

Reference29 articles.

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1. Design of multiplier for arithmetic-high-level synthesis using modified booth encoding;Materials Today: Proceedings;2020-12

2. A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-02

3. FPGA-Based Parallel Implementation of Morphological Operators for 2D Gray-Level Images;Arabian Journal for Science and Engineering;2017-02-07

4. A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier;IEEE Transactions on Computers;2016-11-01

5. Multistage Function Speculation Adders;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2015

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