1. A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% pb-free packaging;Mistry,2007
2. Direct evidence of GeO volatilization from GeO2/Ge and impact of its suppression on GeO2/Ge metal–insulator–semiconductor characteristics;Kita;Japan. J. Appl. Phys.,2008
3. Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces;Prabhakaran;Appl. Phys. Lett.,2000
4. High-k/Ge MOSFETs for future nanoelectronics;Kamata;Mater. Today,2008
5. Advanced Gate Stacks for High-Mobility Semiconductors;Dimoulas,2007