1. M.A. Gaynes et al., High density integrated circuit packaging with chip stacking and via interconnections, US 6002177 A, 1999.
2. J. Knickerbocker et al., 3D silicon integration, in: 58th IEEE Electronic Components and Technology Conference (ECTC), 2008, pp. 538–543.
3. E. Kälvesten et al., Electrical connections in substrates, US7560802 B2, 2009.
4. T. Bauer, High density through wafer via technology, in: NSTI-Nanotech 2007, vol. 3, 2007, p. 116.