Enabling design and simulation of massive parallel nanoarchitectures

Author:

Frache S.,Chiabrando D.,Graziano M.,Vacca M.,Boarino L.,Zamboni M.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference39 articles.

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3. Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures;Martina;IEEE Trans. Circuits Syst. I,2010

4. Quantum dot cellular automata check node implementation for ldpc decoders;Awais;IEEE Trans. Nanotechnology,2013

5. J. Dai, et al., Defect tolerance for molecular electronics-based nanofabrics using built-in self-test procedure, in: IEEE International Symposium on Nanoscale Architecture, 2007.

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