Cache simulation for irregular memory traffic on multi-core CPUs: Case study on performance models for sparse matrix–vector multiplication

Author:

Trotter James D.,Langguth Johannes,Cai Xing

Funder

Research Council of Norway

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Modelling Data Locality of Sparse Matrix-Vector Multiplication on the A64FX;Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis;2023-11-12

2. The Effects of Wide Vector Operations on Processor Caches;2020 IEEE International Conference on Cluster Computing (CLUSTER);2020-09

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