Enhancing scalability in best-effort hardware transactional memory systems

Author:

Quislant RicardoORCID,Gutierrez EladioORCID,Zapata Emilio L.,Plata Oscar

Funder

Government of Spain

Junta de Andalucía

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Achieving Forward Progress Guarantee in Small Hardware Transactions;IEEE Computer Architecture Letters;2024-01

2. Synchronization Strategies on Many-Core SMT Systems;2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD);2021-10

3. DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory;IEEE Transactions on Parallel and Distributed Systems;2021

4. Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactions;Journal of Parallel and Distributed Computing;2019-09

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