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A hardware/software co-design methodology for in-memory processors

  • Published:2022-03 Issue: Volume:161 Page:63-71
  • ISSN:0743-7315
  • Container-title:Journal of Parallel and Distributed Computing
  • language:en
  • Short-container-title:Journal of Parallel and Distributed Computing

Author:

Yantır Hasan ErdemORCID,Eltawil Ahmed M.ORCID,Salama Khaled N.ORCID

Funder

National Institutes of Health

Defense Advanced Research Projects Agency

National Science Foundation

King Abdullah University of Science and Technology

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference53 articles.

1. A scalable processing-in-memory accelerator for parallel graph processing;Ahn;SIGARCH Comput. Archit. News,2015

2. Energy efficient implementation of parallel cmos multipliers with improved compressors;Baran,2010

3. Stratus: free design of highly parametrized vlsi modules interoperable with commercial tools;Belloeil-Dupuis,2011

4. Design of efficient content addressable memories in high-performance finfet technology;Bhattacharya;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2015

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