Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software
Reference8 articles.
1. Networks on chips: A new SoC paradigm;Benini;IEEE Computer,2002
2. K. Bondalapati, V.K. Prasanna, Hardware object selection for mapping loops onto reconfigurable architectures, in: Proc. Int’l. Conf. Par.& Distr. Proc. Tech. and App., 1999
3. H.M. El-Boghdadi, R. Vaidyanathan, J.L. Trahan, S. Rai, On the communication capability of the self-reconfigurable gate array architecture, in: Procs. 9th Reconfigurable Architectures Workshop (RAW 2002), included in Procs. 16th Int. Parallel & Distributed Proc. Symp., Florida, April 15, 2002
4. X.Y. Lin, Y.C. Chung, T.Y. Haung, A multiple LID routing scheme for fat-tree based infiniband networks, in: Proc. Int. Parallel and Distrib. Proc. Symp., 2004
5. Yan Lin, Fei Li, Lei He, Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability, in: Proc. Field Programmable Gate Arrays (FPGAs) ’05, Monterey, California, USA, February 20–22, 2005
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献