Faster optimal parallel prefix circuits: New algorithmic construction

Author:

Lin Yen-Chun,Su Chin-Yu

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference45 articles.

1. Parallel Computation: Models and Methods;Akl,1997

2. Parallel biological sequence comparison using prefix computaions;Aluru;J. Parallel Distrib. Comput.,2003

3. A heuristic for suffix solutions;Bilgory;IEEE Trans. Comput.,1986

4. Scans as primitive operations;Blelloch;IEEE Trans. Comput.,1989

5. A regular layout for parallel adders;Brent;IEEE Trans. Comput.,1982

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1. Optimization of Microarchitecture and Dataflow for Sparse Tensor CNN Acceleration;IEEE Access;2023

2. Analysis of Parallel Prefix Adders with Low Power and Higher Speed;2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC);2022-08-17

3. SparTen;Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture;2019-10-12

4. Dynamic-width reconfigurable parallel prefix circuits;The Journal of Supercomputing;2015-01-01

5. Dynamic-Width Reconfigurable Parallel Prefix Circuits;2013 IEEE 16th International Conference on Computational Science and Engineering;2013-12

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