Dynamic-width reconfigurable parallel prefix circuits
Author:
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Information Systems,Theoretical Computer Science,Software
Link
http://link.springer.com/content/pdf/10.1007/s11227-014-1270-2.pdf
Reference18 articles.
1. Akl SG (1997) Parallel computation: models and methods. Prentice-Hall, Upper Saddle River
2. Leighton FT (1992) Introduction to parallel algorithms and architectures: arrays, trees. Hypercubes. Morgan Kaufmann, San Mateo
3. Datta A (2004) Multiple addition and prefix sum on a linear array with a reconfigurable pipelined bus system. J Supercomput 29(3):303–317
4. Hagerup T (1995) The parallel complexity of integer prefix summation. Inform Process Lett 56(1):59–64
5. Hsu WJ, Page CV (1995) Parallel tree contraction and prefix computations on a large family of interconnection topologies. Acta Inform 32(2):145–153
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