Author:
Bychikhin S.,Dubec V.,Litzenberger M.,Pogany D.,Gornik E.,Groos G.,Esmark K.,Stecher M.,Stadler W.,Gieser H.,Wolf H.
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Biotechnology,Electronic, Optical and Magnetic Materials
Reference31 articles.
1. ESD in integrated circuits;Amerasekera;Qual. Rel. Eng. Int.,1992
2. Grounded-gate nMOS transistor behavior under CDM ESD stress conditions;Verhaege;IEEE Trans. Electron Devices,1997
3. W. Wilkening, W. Stadler, J. Willemen, K. Esmark, H. Wolf, H. Gieser, Investigations on charged device model for on-chip protection in the ASDESE project, Proceedings of the 7th ESD Forum’2001, Berlin, 2001, pp. 87–94.
4. Very fast transmission line pulsing of integrated structures and the charged device model;Gieser;IEEE Trans. Comp. Pack. Manuf. Tech. C,1998
5. Simulation study from the CDM ESD behaviour of the grounded-gate NMOS;Russ;Microel. Reliab.,1996
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